Digitally modulated high-frequency test signals are often required in communication systems for transmission measurement and verification purposes. Wireless communications are rapidly becoming a major sector of the communication industry. Therefore there is a constantly growing demand for vector signal generators capable of synthesizing a diversified set of modulated test signals in a radio frequency (RF) range.
A conventional approach to high-frequency test signal generation (including an IQ modulated signal generation) is to use an arbitrary waveform generator (AWG) having a structure as shown in FIG. 1, where a waveform memory 100 stores a set of precomputed samples (e.g., loaded from a control computer) that represents a desired signal. The samples are provided from the memory 100 to a digital to analog converter (DAC) 103 through a sample bus 102. The DAC 103 produces an analog signal according to the received sequence of digital samples. The analog signal is then passed through a low pass filter 104 that suppresses the spurious frequency components. Such a structure is used, for example, in an arbitrary waveform generator AWG-7000 designed by Tektronix Inc.
There are some disadvantages associated with the AWG shown in FIG. 1. It is not possible to use external data sources. In addition, the length of signal waveforms that can be generated is limited by the size of the waveform memory 100. Once the number of signal waveform segments exceeds the size of the waveform memory, it is not possible to add new segments. Attempts have been made to overcome the limitations related to the waveform memory size by utilizing sequencers to control the playback of the repetitive signal waveforms from the memory. Unfortunately, in many situations, since the sequences of signal waveform segments are similar but not identical, a sequencer is often not effective in terms of compressing the volume of the signal waveforms in the memory. Moreover, this approach does not allow programmable modifications to be made to the signal waveform such as frequency, phase shift or gain changes.
Another feature associated with a conventional AWG as shown in FIG. 1 is that the waveform memory 100 is connected directly to the DAC. This gives rise to another difficulty because it makes it difficult to change the carrier frequency of the modulated signal. It requires reloading of the waveform memory which is time consuming. When it is accompanied by a change in the DAC sampling frequency, then a simultaneous change of the low pass filter located after the DAC is also necessary. The necessity to include into the device a set of interchangeable filters makes it much more cumbersome and expensive.
Another approach to high-frequency test signal generation is to incorporate an IQ modulator in the signal generator and the output signal of the IQ modulator is converted to a desired RF frequency (see, for example, the U.S. Pat. No. 7,212,585, entitled “Quadrature modulation transmitter”). The advancement in FPGA technology made it possible to design a completely digital IQ modulator. A block diagram having a structure of a vector signal generator with a digital IQ modulator is shown in FIG. 2. A memory 200 is used as a initial signals source to produce I and Q symbol sequences. The memory 200 may store either the symbols themselves to be read out or data to be converted into IQ symbols via coding and mapping. The I and Q outputs from the memory 200 are connected to the interpolation filters 201 and 202 where the sampling rate of the signals can be increased up to a frequency that matches the DAC 207 clock frequency. The interpolated signals from the interpolation filters 201 and 202 are mixed with the sine and cosine carriers from a numerically controlled oscillator NCO 206 in mixers 203 and 204. The outputs of the mixers are then summed in the adder 205 and applied to the digital to analog converter DAC 207. The low pass filter LPF 208 suppresses the spurious high frequency products in the analog signal from DAC output, creating in that way an intermediate frequency (IF) modulated signal. The frequency up converter 209 transfers the IF signal to the RF range for further transmission.
The weak point of the arrangement in FIG. 2 is the up converter 209. The requirements to the up converter are self-contradictory: it is necessary to provide both high accuracy of frequency transfer set up and low phase noise introduced in the transferred signal. In addition, there are problems associated with non-linearity distortions, spurious products appearance and the need for expensive components such as carrier Direct Digital Synthesis (DDS). When the DAC clock frequency is relatively low (in the range of 100 MHz), it may be difficult to suppress un-used side band in the up converter.
Suggestions have been made to utilize direct RF signal digital synthesis that eliminates the IF stage and above mentioned disadvantages (see, for example, the U.S. Pat. No. 5,412,352, entitled “Modulator having direct digital synthesis for broadband RF transmission”). Although the proposed solution addressed the drawbacks of the vector signal generator with the up converter, since the signal processing rate was bounded by FPGA ratings, the output signal frequency range was only in the range of 5-40 MHz.
Thus, there is a need for a vector signal generator that is free from the above mentioned disadvantages, where a direct digital RF signal synthesis with present day rates of digital signal processing in a regular FPGA (about 120-250 MHz) combined with high frequency DAC, which makes it possible to generate modulated signal in high frequency RF range (up to 11 GHz and higher).